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AI Can Generate Verification Code. But Can It Prove It Works? It's Time to Find Out.

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AI Can Generate Verification Code. But Can It Prove It Works? It's Time to Find Out.

Moores Lab AI Launches a New Benchmarking Platform to Put Human- and AI-Generated Design Verification to the Test

AI is generating semiconductor code faster than ever. But faster code generation doesn't necessarily mean better verification—or faster tapeout. A testbench that compiles isn't necessarily a testbench that catches bugs. An assertion that looks correct may miss critical design behavior. And a verification environment that appears complete may leave costly coverage gaps undiscovered until late in the development cycle. In his recent Tech Talk, What Generic AI Tools Get Wrong About Design Verification, Moores Lab AI CEO and Co-Founder Shelly Henry highlighted the fundamental disconnect between what general-purpose large language models produce and what semiconductor engineers actually need: verification collateral grounded in design intent, capable of detecting real bugs, and supported by measurable evidence. The challenge isn't generating more code. It's knowing whether that code is good enough to trust.

This question is rapidly becoming central to the semiconductor industry's AI conversation. NVIDIA and ChipAgents recently introduced Build-A-Chip-Bench, an initiative evaluating whether AI agents can successfully navigate the chip design process from specification to physical implementation. Early results reported by ChipAgents showed that evaluated agents passed functional verification on approximately 40% of tasks, while only about 10% met the required physical performance, power, and area targets. The message is clear: producing plausible RTL is not the same as delivering a verified design. Discussions on SemiWiki, including an ESD Alliance panel featuring leaders from Moores Lab AI, ChipAgents, Breker Verification Systems, and others, have reinforced the need for objective benchmarks that measure correctness, coverage, and reliability rather than simply code generation speed. The industry is moving from asking what AI can generate to demanding proof of what AI can deliver.

Today, Moores Lab AI is bringing that challenge directly to the design verification community with the official launch of our new Verification Collateral Benchmarking Platform. Built for DV engineers, the platform creates a hands-on environment where human expertise and AI-generated verification work can be evaluated against common engineering challenges. Participants can work with standardized IP designs, download specifications and RTL, develop their verification collateral, and submit their work for evaluation against a published scoring rubric. Rather than relying on subjective claims about code quality, engineers receive scores and evidence-based feedback that help them understand how their submissions perform and where improvements are needed. A shared leaderboard adds another dimension: the opportunity to compare approaches, challenge peers, and demonstrate verification skills through measurable results.

Why does this matter? Because in semiconductor development, the cost of discovering a problem grows when that problem survives into later stages of the design cycle. Weak testbenches, missed corner cases, incomplete checking, and insufficient verification coverage can translate into additional debugging cycles, schedule delays, engineering expense, and potentially costly silicon respins. As AI-generated verification collateral becomes more common, engineering teams need better ways to evaluate whether that output is genuinely useful before depending on it in production workflows. Benchmarking provides a practical starting point: consistent challenges, transparent evaluation criteria, and actionable feedback that expose weaknesses earlier. It also gives engineers a way to determine where AI accelerates meaningful verification work, where human expertise remains essential, and how the two can work together to improve outcomes.

At Moores Lab AI, we believe the future of semiconductor engineering depends on measurable quality, not just automation. Our work across specification analysis, verification generation, debugging, and coverage closure is built around a simple principle: engineering results must be validated, not assumed. The Benchmarking Platform extends that philosophy to the broader DV community. Whether you're an experienced verification engineer, a student building your skills, a researcher developing AI models, or a semiconductor team exploring AI-assisted workflows, this is an opportunity to put verification approaches to the test, learn from objective feedback, and contribute to a more transparent standard for evaluating verification quality. The goal is not to declare that humans or AI are inherently better. It's to discover what actually works—and use that evidence to advance the entire industry.

Now it's your turn to prove it. Think your verification code can catch the bugs others miss? Want to see how your AI-generated testbench measures up against human-developed work? Ready to challenge yourself against other DV engineers? The Moores Lab AI Benchmarking Platform is your opportunity to move beyond claims and put your work to the test. Download the design specifications, build your verification collateral, submit your results, and see where you stand on the leaderboard. Because the future of semiconductor verification won't be determined by who generates the most code. It will be determined by who can prove their code delivers.