AI can generate SystemVerilog and UVM code that looks right. But does it catch the corner cases, model protocol behavior, and close coverage the way production design verification demands? In his Tech Talk from Verification Futures in Austin this fall, Moores Lab AI CEO Shelly breaks down the gap with real AXI4 examples, showing where AI falls short, what engineers still need to get right, and what it takes to move from plausible code to trustworthy verification.
The AI verification gap is especially clear in AI-generated SystemVerilog and UVM code, where plausible-looking outputs can miss critical protocol behavior, corner cases, and functional coverage requirements. In this talk, Shelly explores the challenges of AI in design verification, AI-generated testbench validation, SystemVerilog assertions, and functional verification, showing why production-ready semiconductor engineering requires more than code that simply looks correct.
